场效应管(MOSFET)_EPC2302_规格书

eGaN® FET DATASHEET EPC2302EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 | | 1
EPC2302XYYWWXXXXEPC2302 – Enhancement Mode Power Transistor
VDS , 100 V
RDS(on) , 1.8 m Ω max
Features
• 100 V
• 1.4 mΩ typical, 1.8 mΩ max RDS(on)
• 3 x 5 mm QFN package
• Exposed top for top-side thermal management
• Moisture rating MSL2
• Enhanced Thermal-Max package
Applications
• AC-DC chargers, SMPS, adaptors, power supplies
• High Frequency DC-DC Conversion up to 80 V
input (Buck, Boost, Buck-Boost and LLC)
• 24 V–60 V Motor Drives
• High Power Density DC-DC modules from
40 V– 60 V to 5 V–12 V
• Synchronous Rectification
• Solar MPPT
Benefits
• Ultra High Efficiency
• No Reverse Recovery
• Ultra Low QG
• Small Footprint
• Excellent ThermalEFFICIENT POWER CONVERSION
HAL
Maximum Ratings
PARAMETER VALUE UNIT
VDSDrain-to-Source Voltage (Continuous) 100
V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150 °C) 120
IDContinuous (T A = 25°C) 101
A
Pulsed (25°C, T PULSE = 300 µs) 408
VGSGate-to-Source Voltage 6
V
Gate-to-Source Voltage -4
TJ Operating Temperature –40 to 150
°C
TSTG Storage Temperature –40 to 150
EPC2302
Package size: 3 x 5 mm General Description
The EPC2302 is a 1.8 mΩ max RDS(on) , 100 V eGaN® power transistor in a low inductance 3 x 5 mm QFN
package with exposed top for excellent thermal management. It is tailored to high frequency DC-DC
applications to/from 40 V–60 V and 48 V BLDC motor drives.
The thermal resistance to case top is ~0.2 °C/W, resulting in excellent thermal behavior and easy
cooling. The device features an enhanced PQFN “Thermal-Max” package. The exposed top enhances
top-side thermal management and the side-wettable flanks guarantee that the complete side-pad
surface is wetted with solder during the reflow soldering process, which protects the copper and
allows soldering to occur on this external flank area for easy optical inspection.
Compared to a Si MOSFET, the footprint of 15 mm2 is less than half of the size of the best-in-class Si
MOSFET with similar Rds(on) and voltage rating, QG and QGD are significantly smaller and QRR is 0.
This results in lower switching losses and lower gate driver losses. Moreover, EPC2302 is very fast
and can operate with deadtime less than 10 ns for higher efficiency and QRR = 0 is a big advantage
for reliability and EMI. In summary, EPC2302 allows the highest power density due to enhanced
efficiency, smaller size, and higher switching frequency for smaller inductor and fewer capacitors.
The EPC2302 enables designers to improve efficiency and save space. The excellent thermal behavior
enables easier and lower cost cooling. The ultra-low capacitance and zero reverse recovery of the
eGaN® FET enables efficient operation in many topologies. Performance is further enhanced due to
the small, low inductance footprint.
Application notes:
• Easy-to-use and reliable gate, Gate Drive ON = 5 V typical, OFF = 0 V (negative voltage not needed)
• Top of FET is electrically connected to source
• Questions: Ask a GaN Expert https://epc-co.com/epc/Contact/AskaGaNExpert.aspxGD
S
Scan QR code or click
link below for more
information including
reliability reports, device
models, demo boards!
https://l.ead.me/EPC2302
eGaN® FET DATASHEET EPC2302EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 | | 2# Defined by design. Not subject to production test.Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.15 mA 100 V
IDSS Drain-Source Leakage VDS = 80 V, V GS = 0 V 1 100 μA
IGSSGate-to-Source Forward Leakage VGS = 5 V 0.01 4
mA Gate-to-Source Forward Leakage#VGS = 5 V, T J = 125 °C 0.4 9
Gate-to-Source Reverse Leakage VGS = -4 V 0.01 0.2
VGS(TH) Gate Threshold Voltage VDS = V GS, ID = 14 mA 0.8 1.3 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, I D = 50 A 1.4 1.8 mΩ
VSD Source-to-Drain Forward Voltage IS = 0.5 A, V GS = 0 V 1.5 VThermal Characteristics
PARAMETER TYP UNIT
RθJC Thermal Resistance, Junction-to-Case (Case TOP) 0.2
°C/W RθJB Thermal Resistance, Junction-to-Board (Case BOTTOM) 1.5
RθJA_JEDEC Thermal Resistance, Junction-to-Ambient (using JEDEC 51-2 PCB) 45
RθJA_EVB Thermal Resistance, Junction-to-Ambient (using EPC90142 EVB) 21
Dynamic Characteristics# (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS Input Capacitance
VDS = 50 V, V GS = 0 V3200 4800
pFCRSS Reverse Transfer Capacitance 7
COSS Output Capacitance 1000 1200
COSS(ER) Effective Output Capacitance, Energy Related (Note 1)
VDS = 0 to 50 V, V GS = 0 V1300
COSS(TR) Effective Output Capacitance, Time Related (Note 2) 1700
RG Gate Resistance 0.5 Ω
QG Total Gate Charge VDS = 50 V, V GS = 5 V, I D = 50 A 23 29
nCQGS Gate-to-Source Charge
VDS = 50 V, I D = 50 A8.9
QGD Gate-to-Drain Charge 2.3
QG(TH) Gate Charge at Threshold 6.3
QOSS Output Charge VDS = 50 V, V GS = 0 V 85 94
QRR Source-Drain Recovery Charge 0
# Defined by design. Not subject to production test.
Note 1: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 2: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
eGaN® FET DATASHEET EPC2302EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 | | 3400
350
300
250
200
150
100
50
0
0 0.5 1.0 1.5 2.0 2.5 3.0 ID – Drain Current (A)Figur e 1: Typic al O utput C harac teristics at 25°C
VDS – Drain-to-Source Voltage (V) VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 VRDS(on) – Drain-to-Sourc e Resista nce (m/uni03A9)
VGS – Gate-to-Source Voltage (V) 3.0 3.5 4.0 4.5 5.0Figur e 3: Typical R DS(on) vs. V GS for Various Drain Curr ents
ID = 25 A
ID = 50 A
ID = 75 A
ID = 100 A6
5
4
3
2
1
01.0 0.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0Figure 2: Typical Transfer Characteristics
25˚C
125˚C
VDS = 3 V ID – Drain Current (A)
VGS – Gate-to-Source Voltage (V) 1.0 0.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.025˚C
125˚C
VDS = 3 V400
350
300
250
200
150
100
50
0
3.0 3.5 4.0 4.5 5.0 Figur e 4: Typical R DS(on) vs. V GS for Various Temperatures
25˚C
125˚C
ID = 50 ARDS(on) – Drain-to-Sourc e Resista nce (m/uni03A9)
VGS – Gate-to-Source Voltage (V) 6
5
4
3
2
1
0 Capacitance (pF)10000
1000
100
10
1
0 25 50 75 100 Figur e 5b: Typical C apacitance (Log Scale)
VDS – Drain-to-Source Voltage (V) COSS = C GD + C SD
CISS = C GD + C GS
CRSS = C GD Capacitance (pF)
0 25 50 75 100Figur e 5a: Typical C apacitance (Linear Scale)
VDS – Drain-to-Source Voltage (V) COSS = C GD + C SD
CISS = C GD + C GS
CRSS = C GD4000
3000
2000
1000
0
eGaN® FET DATASHEET EPC2302EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 | | 45
4
3
2
1
00 5 10 15 20 25Figur e 7: Typical Gate ChargeVGS – Gate-to-Source Voltage (V)
QG – Gate Charge (nC)ID = 50 A
VDS = 50 V
Figur e 9: Typical N ormaliz ed O n-State R esistance vs. Temp.
ID = 50 A
VGS = 5 VNormalized On-State Resistance R DS(on)2.5
2.0
1.5
1.0
0.5
0 25 50 75 100 125 150
TJ – Junction Temperature (°C) QOSS – Output charge (nC)
EOSS — C OSS Stored Energy (µ J)120
90
60
30
00 20 40 60 80 100 5.00
3.75
2.50
1.25
0.00Figur e 6: Typical Output Charge and C OSS Stored Energy
VDS – Drain-to-Source Voltage (V)
0.5 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ISD – Source-to-Drain Current (A)
VSD – Source-to-Drain Voltage (V)Figur e 8: Typical R everse D rain-S ource C harac teristics
25˚C
125˚C
VGS = 0 V400
350
300
250
200
150
100
50
0
Figur e 10: Typical N ormaliz ed Threshold Voltage vs. Temp.Normalized Threshold Voltage1.50
1.25
1.00
0.75
0.50
0 25 50 75 100 125 150
TJ – Junction Temperature (°C) ID = 14 mA1000
100
10
1
0.1
0.1 1 10 100 1000 ID – Drain Current (A)
VDS – Drain-Source Voltage (V)
TJ = Max Rated, TC = +25°C, Single Pulse Limited by R DS(on)
100 ms
10 ms
1 ms
100 µs Pulse Width
1 ms
10 µs 100 µs Figur e 11: Safe Operating Area
eGaN® FET DATASHEET EPC2302EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 | | 5Figure 12: Transient Thermal Response Curves
1
tp – Rectangular Pulse Duration (s)ZθJB, Normalized Thermal ImpedanceDuty Factors:
0.5
0.1
0.05
0.02
0.01
Single Pulse0.2
Notes:
Duty Factor = t p/T
Peak T J = P DM x Z θJB x R θJB + T Btp PT
DM Junction-to-Board
10-5 10-4 10-3 10-2 10-1 100.1
0.0010.01
1
tp – Rectangular Pulse Duration (s)ZθC, Normalized Thermal ImpedanceJunction-to-Case
Duty Factors:
0.5
0.1
0.05
0.02
0.01
Single Pulse0.2
Notes:
Duty Factor = t p/T
Peak T J = P DM x Z θJC x R θJC + T Ctp PT
DM
10-5 10-6 10-4 10-3 10-2 10-1 10.0011
0.010.1
eGaN® FET DATASHEET EPC2302EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 | | 6
w2
A
N
D
Cw1
T
Type A N C D w1 w2 T
8MM Ø330±2 Ø100±2 Ø13.1±0.2 5.6±0.5 8.4+1.5 14.4 2.1±0.5
12MM Ø330±2 Ø100±2 Ø13.1±0.2 5.6±0.5 12.4+1.5 18.4 2.1±0.5
16MM Ø330±2 Ø100±2 Ø13.1±0.2 5.6±0.5 16.4+1.5 22.4 2.1±0.5
24MM Ø330±2 Ø100±2 Ø13.1±0.2 5.6±0.5 24.4+1.5 30,4 2.1±0.5Top View Bottom View
Side View
Bottom View DetailLoaded tape
feed direction
Top View DetailTAPE AND REEL
(units in mm)
eGaN® FET DATASHEET EPC2302EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 | | 7Notes:
1. Dimensioning and tolerancing conform to
ASME Y14.5-2009
2. All dimensions are in millimeters
3. N is the total number of terminals
4. Dimension b applies to the metallized
terminal. If the terminal has a radius on the
other end of it, dimension b should not be
measured in that radius area.
5. Coplanarity applies to the terminals and all the
other bottom surface metallization.SYMBOLDimension (mm)
MIN Nominal MAX Note
A 0.60 0.65 0.70
A1 0.00 0.02 0.05
A3 0.20 Ref
b 0.20 0.25 0.30 4
b1 0.30 0.35 0.40 4
b2 0.20 0.25 0.30 4
D 3.00 BSC
E 5.00 BSC
e 0.85 BSC
e1 0.90 BSC
L1 0.625 0.725 0.825
L2 1.775 1.875 1.975SYMBOLDimension (mm)
MIN Nominal MAX Note
K 0.35 0.40 0.45
K1 0.10 0.15 0.20
K2 0.55 0.60 0.65
K3 0.35 0.40 0.45
K4 0.25 0.30 0.35
aaa 0.05
bbb 0.10
ccc 0.10
ddd 0.05
eee 0.08
N 15 3
NE 6EPC2301XYYWWXXXX
D 0.05
Max. 2.600
Die sizeSite/date code
Lot code
A
B
AA3
Top ViewExposed
die
Bottom View Side View 1Side View 2
C aaa 2xC aaa 2×0.10 Max.
Seating planeA
A3 A1C eee5CC// ccc
4.470
Die
sizeE
5.007
6
5
4
3
2 1bbb C4
L1 L2Ke1
K2
Ne
K40.150 Chamferb (4x)b2 (8x)
b1 (3x)K1 (3x)K3 (4x)
CAB M
ddd MEPC2302XYYWWXXXX1
234567
Pad 1 is Gate ;
Pads 2, 4. 6 are Source ;
Pads 3, 5, 7 are Drain
eGaN® FET DATASHEET EPC2302EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 | | 87
6
5
4
3
2 1PIN Description
1 Gate
2 Source
3 Drain
4 Source
5 Drain
6 Source
7 Drain
RECOMMENDED
LAND PATTERN
(units in mm)TRANSPARENT VIEW
Land pattern is solder mask defined.
It is recommended to have on-Cu trace PCB vias.
R50d2
e
Bg
c5d1c1
f/uni00A0
d2h
Ac2
c3c4
c3
c4DIM Nominal
A 5.4
B 3.4
c1 2.11
c2 0.91
c3 0.54
c4 1.19
c5 0.985
d1 0.47
d2 0.37
e 0.85
f 0.29
g 0.2
h 0.06
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its
patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspxInformation subject to
change without notice.
Revised March, 2023Additional resources available:
• Assembly resources – https://epc-co.com/epc/Portals/0/epc/documents/product-training/Appnote_GaNassembly.pdf
• Library of Altium footprints for production FETs and ICs – https://epc-co.com/epc/documents/altium-files/EPC%20Altium%20Library.zip
(for preliminary device Altium footprints, contact EPC)